VMULSH—Multiply Scalar FP16 Values

Opcode/Instruction Op/En 64/32 bit Mode Support CPUID Feature Flag Description
EVEX.LLIG.F3.MAP5.W0 59 /r VMULSH xmm1{k1}{z}, xmm2, xmm3/m16 {er} A V/V AVX512-FP16 Multiply the low FP16 value in xmm3/m16 by low FP16 value in xmm2, and store the result in xmm1 subject to writemask k1. Bits 127:16 of xmm2 are copied to xmm1[127:16].

Instruction Operand Encoding

Op/En Tuple Operand 1 Operand 2 Operand 3 Operand 4
A Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A


This instruction multiplies the low FP16 value from the source operands and stores the FP16 result in the destina-tion operand. Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according to the writemask.


VMULSH (EVEX encoded versions)

IF EVEX.b = 1 and SRC2 is a register:




IF k1[0] OR *no writemask*:

DEST.fp16[0] := SRC1.fp16[0] * SRC2.fp16[0]

ELSE IF *zeroing*:

DEST.fp16[0] := 0

// else dest.fp16[0] remains unchanged

DEST[127:16] := SRC1[127:16]


Intel C/C++ Compiler Intrinsic Equivalent

VMULSH __m128h _mm_mask_mul_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int rounding);

VMULSH __m128h _mm_maskz_mul_round_sh (__mmask8 k, __m128h a, __m128h b, int rounding);

VMULSH __m128h _mm_mul_round_sh (__m128h a, __m128h b, int rounding);

VMULSH __m128h _mm_mask_mul_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);

VMULSH __m128h _mm_maskz_mul_sh (__mmask8 k, __m128h a, __m128h b);

VMULSH __m128h _mm_mul_sh (__m128h a, __m128h b);

SIMD Floating-Point Exceptions

Invalid, Underflow, Overflow, Precision, Denormal

Other Exceptions

EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”