|64/32 bit Mode Support
|CPUID Feature Flag
|F2 0F 38 F8 !(11):rrr:bbb ENQCMD r32/r64, m512
|Atomically enqueue 64-byte user command from source memory operand to destination offset in ES segment specified in register operand as offset in ES segment.
The ENQCMD instruction allows software to write commands to enqueue registers, which are special device registers accessed using memory-mapped I/O (MMIO).
Enqueue registers expect writes to have the following format:
Bits 19:0 convey the process address space identifier (PASID), a value which system software may assign to indi-vidual software threads. Bit 31 contains privilege identification (0 = user; 1 = supervisor). Devices implementing enqueue registers may use these two values along with a device-specific command in the upper 60 bytes.
The ENQCMD instruction begins by reading 64 bytes of command data from its source memory operand. This is an ordinary load with cacheability and memory ordering implied normally by the memory type. The source operand need not be aligned, and there is no guarantee that all 64 bytes are loaded atomically. Bits 31:0 of the source operand must be zero.
The instruction then formats those 64 bytes into command data with a format consistent with that given in Figure 3-16:
The ENQCMD instruction uses an enqueue store (defined below) to write this command data to the destination operand. The address of the destination operand is specified in a general-purpose register as an offset into the ES segment (the segment cannot be overridden).2 The destination linear address must be 64-byte aligned. The oper-ation of an enqueue store disregards the memory type of the destination memory address.
It is expected that system software will load the IA32_PASID MSR so that bits 19:0 contain the PASID of the current soft-ware thread. The MSR’s valid bit, IA32_PASID, must be 1. For additional details on the IA32_PASID MSR, see the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4.